1. Field of the Invention
This invention generally relates to a semiconductor integrated circuit device and a method of manufacturing the same and, more particularly, it relates to a technology that is effectively applicable to the manufacture of a semiconductor integrated circuit device in order to enhance the storage capacitance of DRAM (dynamic random access memory).
2. Description of the Prior Art
In a DRAM, the memory cells are disposed on the respective crossings of the word lines and the bit lines arranged in the form of matrix on the main surface of the semiconductor substrate, each memory cell comprising a MISFET (Metal Insulator Semiconductor Field Effect Transistor) to be used for selecting the memory cell and an information storage capacitor. The memory cell selecting MISFET is formed in an active region surrounded by a device isolation region and comprises as main components thereof a gate oxide film, a gate electrode integral with the corresponding word line and a pair of semiconductor regions constituting a source and a drain. The corresponding bit line is located above the memory cell selecting MISFET and electrically connected to either the source or the drain shared by the memory cell selecting MISFET and another memory cell selecting MISFET located adjacent to it. The information storage capacitor is also located above the memory cell selecting MISFET and electrically connected to the drain or the source not shared by the two MISFETs.
Japanese Patent Application Laid-Open No. 7-7084 discloses a DRAM having a so-called capacitor over bit line (COB) structure of arranging information storage capacitors above bit lines. In the disclosed DRAM, the lower electrodes (storage electrodes) of the information storage capacitors arranged above the bit lines are made to have a cylindrical profile to raise the surface area thereof in order to compensate the reduction in the stored electric charge (Cs) of the information storage capacitors given rise to by the extremely reduced size of the memory cells and the capacitor insulator and the upper electrode (plate electrode) of each memory cell is arranged above the information storage capacitor.
Japanese Patent Applications Laid-Open Nos. 64-42161 and 1-187847 disclose a technique of producing fine undulations on the surface of the lower electrodes of the information storage capacitors to raise the surface area thereof and secure the necessary storage capacitance by using poly-crystalline silicon for the lower electrodes and utilizing the phenomenon that the growth of granular poly-crystalline silicon depends on the surface condition of the under-layer in the initial stages of forming the poly-crystalline silicon by means of chemical vapor deposition (hereinafter referred to as CVD) or that the difference of the etching rate between boundary and bulk of the poly-crystalline silicon.
Finally, Japanese Patent Application Laid-Open No. 8-167702 discloses a technique of securing the necessary storage capacitance of an information storage capacitor comprising a first electrode (lower electrode) having a fin structure, a second electrode (upper electrode) and a dielectric material formed between the first and second electrodes by forming the first electrode from a material containing ruthenium oxide and the dielectric material from a material containing tantalum pentoxide so that the storage capacitance of the capacitor may be secured by the high dielectric constant of the material containing tantalum pentoxide.
However, the demand for a higher degree of integration gives rise to an ever-increasing demand for memory cells occupying a smaller area that cannot be met by the technique of raising the surface area of the lower electrode of each information storage capacitor by giving a cylindrical profile to it as proposed by Japanese Patent Application Laid-Open No. 7-7084 nor by forming fine undulations on the surface as proposed by Japanese Patent Applications Laid-Open Nos. 64-42161 and 1-187847. Thus, there is a demand for a technique of increasing the surface area of the lower electrode that cannot be met by simply providing it with a cylindrical profile because the height of the cylinder is limited by the mechanical strength required to the lower electrode and the stepped arrangement of the memory cell array region and the periphery circuit region due to the height of the lower electrodes nor by forming fine undulations on the surface of the lower electrode because they depend on the surface condition and the physical properties of the silicon of the device.
As for the technique of using a material having a high dielectric constant such as tantalum pentoxide for the capacitor insulator of the information storage capacitor disclosed by Japanese Patent Application Laid-Open No. 8-167702, the capacitor insulator is made of tantalum oxide film having a film thickness of 2.5 nm or more as expressed in terms of equivalent thickness of silicon oxide film. However, it is not possible for the technique to secure the capacitance required for the memory cells of a 256 Mbits DRAM or those of a DRAM of a later generation. Thus, there still remains the problem of securing a sufficient effective surface area if lower electrodes having a fin structure are used.
Additionally, if the capacitor insulator is made of tantalum oxide film, it is difficult to use silicon (poly-crystalline silicon film) for the lower electrode because, if silicon is exposed to an oxygen containing atmosphere during the process of forming tantalum oxide, a silicon oxide film having a low dielectric constant is formed along the interface of the lower electrode and the tantalum oxide film to increase the effective film thickness of the capacitor insulator and, therefore, decrease the effective dielectric constant of the capacitor insulator to reduce the stored electric charge. In view of this problem, Japanese Patent Application Laid-Open No. 8-167702 proposes the use of ruthenium oxide for the lower electrode as a material that can prevent the generation of a low dielectric constant layer.
However, if the typical process of depositing ruthenium by sputtering and subsequently oxidizing the deposited ruthenium layer is used to produce ruthenium oxide, undulations appear on the surface of the ruthenium oxide film to damage the reliability of the information storage capacitor.
In view of the above identified problems of the prior art, it is therefore an object of the present invention to provide a technology that can effectively secure a required storage capacitance for the information storage capacitors of the memory cells of a 256 Mbits DRAM or a DRAM of a later generation.
Another object of the present invention is to provide a technology that makes it possible to use tantalum oxide for the capacitor insulator of information storage capacitor without lowering the effective dielectric constant of the capacitor insulator and raising the film thickness of the insulator if thermally treated in an oxygen containing atmosphere.
Still another object of the present invention is to provide a technology of planarizing the surface of the lower electrode of information storage capacitor to improve the reliability of the information storage capacitor.
Still another object of the present invention is to provide a technology that makes it possible to simplify the profile of the lower electrode and the process of producing it.
A further object of the present invention is to provide a technology of improving the insulation effect of the capacitor insulator of information storage capacitor and reduce the leak current in order to improve the performance and the reliability of the information storage capacitor.
A further object of the present invention is to optimize the material of the upper electrode of information storage capacitor and provide a highly reliable information storage capacitor.
A still further object of the present invention is to raise the stored electric charge of the information storage capacitors of the memory cells of a DRAM and thereby raise the refresh margin of the DRAM in order to realize a semiconductor integrated circuit device adapted to a low supply voltage and a low power consumption rate.
The above objects and further object of the invention and the novel features of the present invention will become appear from the following description made by referring to the accompanying drawings.
Firstly, some aspects of the present invention will be briefly summarized.
According to an aspect of the invention, there is provided a semiconductor integrated circuit device including a memory cell comprising a memory cell selecting MISFET formed on the main surface of a semiconductor substrate and an information storage capacitor that is connected in series to said memory cell selecting MISFET and that have a lower electrode, a capacitor insulator and an upper electrode, wherein the lower electrode is made of a conductive material containing ruthenium dioxide (RuO2) as principle ingredient and the capacitor insulator is made of crystallized tantalum pentoxide (Ta2O5).
With a semiconductor integrated circuit device having a configuration as described above, no film having a low dielectric constant such as silicon oxide will be produced along the interface of the lower electrode and the capacitor insulator if the latter is made of tantalum pentoxide that is prepared in an oxygen containing atmosphere because the lower electrode is made of a conductive material containing ruthenium dioxide as principal ingredient so that the capacitor insulator can show a high effective dielectric constant and be prevented from undesirably increasing its effective film thickness. It should be stressed here that no film having a low dielectric constant such as silicon oxide film will be produced along the interface of the lower electrode and the capacitor insulator if the tantalum pentoxide of the capacitor insulator is heat treated in an oxygen containing atmosphere in a manner as will be described hereinafter to enhance the extent of crystallization of the tantalum oxide. Since only ruthenium dioxide (RuO2) is stable among the possible oxides of ruthenium, ruthenium dioxide (RuO2) that is stable and electrically conductive is produced with any method of oxidizing ruthenium to provide an effect of broadening the process choice. For instance, if titanium nitride is used for the lower electrode, titanium oxide film is produced along the interface of the titanium nitride film and the tantalum oxide film to undesirably raise the effective film thickness of the capacitor insulator when the interfacial product is electrically nonconductive due to the stoichiometry of the product, although the produced titanium oxide may be electrically conductive and provide no problem depending on its stoichiometry. On the other hand, no such problem occurs when ruthenium oxide is used for the lower electrode according to the invention.
Additionally, the capacitor insulator of a semiconductor integrated circuit device according to the invention is made of crystalline tantalum pentoxide (Ta2O5) having a specific dielectric constant of 40 to 50 much higher than that of non-crystalline tantalum oxide (20 to 25) so that each information storage capacitor can show a storage capacitance far greater than its counterpart using a non-crystalline capacitor insulator if a same film thickness is used. Therefore, the lower electrode does not have to have a fin structure or cylindrical profile to secure a capacitance required to each information storage capacitor of a 256 Mbits DRAM or a 1 Gbits DRAM.
Preferably, in a semiconductor integrated circuit device according to the invention, the lower electrode has a surface roughness of 1 nm or less as expressed in terms of the center line average roughness (Ra).
With a semiconductor integrated circuit device comprising lower electrodes having a surface roughness of 1 nm or less as expressed in terms of the center line average roughness (Ra), each capacitor insulator can secure a sufficient level of planeness relative to the film thickness (5 to 15 nm). If the lower electrode has undulations of about Ra=20 nm on the surface, the capacitor insulator can show an undesirably concentrated electric field and/or areas having a thin film thickness to reduce the withstand voltage. However, with the above arrangement of the present invention, no such problem occurs with a semiconductor integrated circuit device according to the invention because the lower electrodes are secured to show a satisfactory level of planeness.
The capacitor insulator contains carbon atoms. This may be inevitable because the capacitor insulator made of tantalum oxide film is produced by CVD using organic tantalum gas. However, the carbon concentration should be held as low as possible to reduce the leak current.
In a semiconductor integrated circuit device according to the invention, the capacitor insulator may be a laminate of two or more than two crystallized tantalum pentoxide film layers. When crystallized, tantalum pentoxide film shows a poly-crystalline state and poly-crystalline thin film contains grain boundaries. Such grain boundaries of poly-crystalline thin film can reduce the withstand voltage typically of the film due to the segregated impurities and/or an imperfect crystal structure of the film. If, however, the capacitor insulator of a semiconductor integrated circuit device according to the invention is a laminate of two ore more than two crystalline tantalum pentoxide film layers, the leak current due to the grain boundaries of one of the layers can be interrupted by the remaining layer(s) to improve the withstand voltage.
In a semiconductor integrated circuit device according to the invention, preferably the capacitor insulator has a film thickness between 5 and 15 nm. Such a film thickness can secure a sufficient withstand voltage and, at the same time, a satisfactorily small equivalent thickness (the film thickness as expressed in terms of silicon oxide film).
In a semiconductor integrated circuit device according to the invention, preferably the upper electrode is made of single layer film or multilayer film of a material selected from titanium nitride (TiN), ruthenium (Ru), ruthenium dioxide (RuO2), tungsten (W) and tungsten nitride (WN).
With a semiconductor integrated circuit device with such an arrangement, the upper electrodes can be optimized in terms of material to make the information storage capacitors show an improved reliability. More specifically, both ruthenium (Ru) and tungsten (W) are less apt to be oxidized than tantalum (Ta) so that if they are brought into direct contact with the tantalum oxide of the capacitor insulator, they would not draw oxygen from the tantalum oxide film to oxidize themselves. Thus, when the upper electrodes are made of either ruthenium or tungsten (or oxide or nitride of either of them), the stoichiometry of the tantalum oxide is secured for a prolonged period of time and the tantalum oxide remains thermally stable to consequently improve the reliability of the information storage capacitors.
On the other hand, the lower electrodes having a COB structure are formed three-dimensionally and hence it is desirable that the coat layer of the upper electrodes shows a good step coverage and a good step burial. Titanium nitride (TiN) shows a good step coverage and a good step burial because it can be formed by CVD using an inorganic or organic gas as raw material. Thus, upper electrodes showing a good step coverage and a good step burial can be formed by using titanium nitride (TiN) as raw material for it. Voids can be produced in the recesses that may be formed depending on the profile of the lower electrodes to consequently damage the reliability of the information storage capacitors if the upper electrodes have a coat showing a poor step coverage and a poor step burial. To the contrary, no such problem occurs when the upper electrodes are made of titanium nitride by CVD.
Then, the upper electrode may be a laminate of a tungsten film layer arranged in contact with the capacitor insulator and a titanium nitride film layer arranged in contact with the tungsten film layer. Such an arrangement provides the upper electrode with both the advantage of thermal stability and that of effectively preventing voids from appearing.
In a semiconductor integrated circuit device according to the invention and having the above described arrangement, preferably the plug for connecting one semiconductor region (e.g., source/drain region) of the memory cell selecting MISFET and the lower electrode is made of a conductive material containing ruthenium dioxide (RuO2) as principal ingredient.
In a semiconductor integrated circuit device according to the invention and having the above described arrangement, still preferably a blocking film is arranged between a plug for connecting one semiconductor region (e.g., a source/drain region) of a memory cell selecting MISFET and a lower electrode, in order to suppress possible oxidation of said plug.
With such an arrangement, any possible production of an electrically non-conductive object typically made of silicon oxide can be effectively prevented from taking place in an area connecting the source/drain region of each memory cell selecting MISFET and the corresponding lower electrode as a result of the heat treatment for forming the capacitor insulator in an oxidizing atmosphere. More specifically, no silicon oxide film will be formed on the plugs because they are made of an electrically conductive material containing ruthenium dioxide (RuO2) as principal ingredient. If, poly-crystalline silicon is used for the plug, it will not be oxidized to produce silicon oxide film when a blocking film is arranged between each plug and the corresponding lower electrode to suppress possible oxidation of the plug. Thus, a reliable electric connection will be established between the source/drain region of each memory cell selecting MISFET and the corresponding lower electrode to improve the reliability of the semiconductor integrated circuit device.
The blocking film may typically be made of titanium nitride.
According to another aspect of the invention, there is provided a method of manufacturing a semiconductor integrated circuit device including a memory cell comprising a memory cell selecting MISFET formed on the main surface of a semiconductor substrate and an information storage capacitor that is connected in series to said memory cell selecting MISFET and that have a lower electrode, a capacitor insulator and an upper electrode, wherein said method comprises (a) a step of forming memory cell selecting MISFETs and bit lines, subsequently depositing ruthenium dioxide (RuO2) on the interlayer insulator covering the bit lines and then patterning the ruthenium dioxide film layer to produce the lower electrodes and (b) a step of depositing non-crystalline tantalum oxide on the lower electrodes, subsequently crystallizing the tantalum oxide by heat treatment and forming the capacitor insulator from crystallized tantalum pentoxide (Ta2O5).
A semiconductor integrated circuit device having a configuration as described above can be successfully manufactured by means of such a manufacturing method. The entire process of manufacturing a semiconductor integrated circuit device according to the invention is rather simple because the lower electrodes have a simplified structure and are produced simply by patterning a ruthenium dioxide film layer in Step (a). Additionally, since the deposited non-crystalline tantalum oxide is crystallized by heat treatment in Step (b), the tantalum oxide film layer to be used for the capacitor insulator is made to show a raised dielectric constant to increase the storage capacitance of the information storage capacitors.
Preferably, the deposition of ruthenium dioxide is performed by sputtering, using ruthenium dioxide (RuO2) as target material. Thus, since a coat is deposited by sputtering, using ruthenium dioxide (RuO2) as starting material, a remarkably plane coat (Ra=less than 1 nm) can be realized to improve the reliability of the information storage capacitors of the DRAM with a manufacturing method according to the invention if compared with the surface roughness (Ra=about 20 nm) of a coat of ruthenium dioxide formed by a conventional method of depositing ruthenium (Ru) and subsequently oxidizing the deposited ruthenium.
Alternatively, the deposition of ruthenium dioxide is performed by reactive sputtering, using ruthenium (Ru) as target material and oxygen-containing gas. With such a technique of employing reactive etching, using ruthenium (Ru) as target material along with oxygen-containing gas, it is also possible to realize a remarkably plane coat (Ra=less than 1 nm) and improve the reliability of the information storage capacitors of the DRAM.
Still alternatively, the deposition of ruthenium dioxide is performed by CVD, using a source gas containing organic ruthenium gas and oxygen. With such a technique of depositing ruthenium dioxide by CVD in a single process using a source gas containing organic ruthenium gas and oxygen, it is also possible to realize a remarkably plane coat (Ra=less than 1 nm) and improve the reliability of the information storage capacitors of the DRAM. Examples of organic ruthenium gas that can be used for the purpose of the invention include trisdipivaloylmethanatoruthenium (Ru((CH3)3CCOCHCOC(CH3)3)3).
Still alternatively, the tantalum oxide is formed by thermal CVD, using a source gas containing pentaalkyltantalum (Ta(CnH2n+1)5) and oxygen (O2) under low pressure at temperature below 50xc2x0 C. With such a technique of employing thermal CVD, using a source gas containing pentaalkyltantalum (Ta(CnH2n+1)5) and oxygen (O2) under low pressure at temperature below 500xc2x0 C., it is possible to improve the step coverage of the capacitor insulator.
For the purpose of the invention, n is preferably 1 or 2 in order to advantageously reduce the carbon concentration contained in the produced tantalum oxide film.
For the purpose of the invention, the heat treatment of the tantalum oxide is performed in an oxidizing atmosphere at 750xc2x0 C. for 10 minutes or at 800xc2x0 C. for 3 minutes. If the heat treatment of the tantalum oxide is performed in an oxidizing atmosphere at 800xc2x0 C. for 3 minutes, the nucleation density of the crystalline process can be raised to reduce the grain size of tantalum oxide crystals and produce a dense capacitor insulator or a coat having a highly uniform film thickness so that consequently the withstand voltage of the information storage capacitors of the DRAM can be significantly improved.
A method of manufacturing a semiconductor integrated circuit device according to the invention may further comprise a step of forming a single layer film or a multilayer film of a material selected from titanium nitride (TiN), ruthenium (Ru), ruthenium dioxide (RuO2), tungsten (W) and tungsten nitride (WN) by deposition and patterning the single layer film or the multilayer film to produce the upper electrodes.
With such a method, a semiconductor integrated circuit device comprising upper electrodes can be manufactured in a simplified manner.
The foregoing and other objects, advantages, manner of operation and novel features of the present invention will be understood from the following detailed description when read in connection with the accompanying drawings.